library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity SHF is
    port(IR_out:     in unsigned  (15 downto 0);		
	      A:      in unsigned  (15 downto 0);        
	      Result: out unsigned (15 downto 0));           
end entity SHF;

architecture build of SHF is
signal ADR: integer range 0 to 7 := 0;
signal amount: integer range 0 to 15 := 0;

begin
    
    amount <= to_integer(IR_out(3 downto 0));
    ADR <= to_integer(IR_out(6 downto 4));

    process(A, amount, ADR)
    begin    
    case ADR is
        when 0 | 4 =>
            Result <= A sll amount;

        when 2 => 
            Result <= A srl amount;

        when 1 | 5 =>    
            Result <= A rol amount;

        when 3 | 7 =>
            Result <= A ror amount;

        when 6 =>
            Result <= A sra amount;
    end case;

    end process;
end build;
